Analyst: DRAM memory, 3D NAND flash memory layout contends with a hundred schools of thought, Changxin and Yangtze River Storage are making rapid progress

On July 5th, TechInsights, a well-known semiconductor analysis organization, held an online seminar on “Memory Process and Integration Challenges: DRAM & NAND” (Memory Process and Integration Challenges: DRAM & NAND).

Dr. Jeongdong Choe, a senior technical analyst with more than 30 years of experience in the memory chip field, shared the development of DRAM and NAND cutting-edge technologies and the possible challenges in the future.

Recently, Samsung has made breakthroughs in the capacity of 128-layer single-stack products (from 256Gb to 256Gb). In this regard, Jeongdong Choe said at the seminar that major players in the world have various degrees of innovation in 3D NAND design, such as Samsung’s COP architecture, SK Hynix’s PUC architecture, Micron’s CuA architecture and so on.

The core competitiveness of Samsung’s 128-layer single-stack 3D NAND lies in the single-stack, which is different from the multi-deck integration of competitors such as Intel, which can maximize the aspect ratio (high aspect ratio) and the alignment of the deck and the deck. , achieved the world’s smallest cell pitch in mass-produced 3D NAND flash products, showing that single-stack technology still has huge development potential.

Several major players in the DRAM market include Samsung, Micron, SK Hynix, plus Nanya Technology (Nanya), PSMC (PSMC) and Changxin Storage (CXMT).

▲ Source: TechInsights

For DDR4, DDR5 and LPDDR5 applications, Samsung, Micron and SK Hynix have released products for the D1z and D1α nodes with cell design rules (D/R) at the 15nm and 14nm levels.

Micron and SK Hynix are still using ArF-i-based double exposure on the D1z node, although some analysts comment that Samsung’s early deployment of EUV technology in this field is too radical. This figure also shows some DRAM process nodes after 2024, including D1d, D0a, D0b, etc.

In addition to DRAM, NAND technology is also ushering in rapid development.

The current progress is Samsung 176-layer (V7), Kioxia/Western Digital 162-layer (BiCS6), Micron 176-layer (2nd CTF), SK Hynix 176-layer (V7), and YMTC’s 128-layer Xtacking TLC and QLC products; In addition, Hongwang (MXIC) also announced a 48-layer 3D NAND prototype product, which is expected to enter mass production later this year or in 2023.

Some main innovative technologies and designs, such as 3-layer deck structure, CuA (CMOS-under-array, Micron), COP (Cell Over Peri, Samsung), PUC (Periphery Under Cell, SK Hynix) structure technology, and adopt H-bonding bonded Xtacking die. Other innovative technology hotspots include low-latency and high-speed NAND products such as Samsung Z-NAND and Kioxia XL-NAND, which have also been commercialized.

In terms of new memory, the current development of STT-MRAM is very good. The companies and institutions involved in the research and development of this technology include Everspin, GlobalFoundries, Avalanche, Sony, Micron, Imec, CEA-LETI, American Applied Materials, Samsung, Fujitsu, IBM, TSMC, Spin Transfer Technologies, etc.