IT House July 9 news, RISC-V is an open source, free instruction set architecture based on the reduced instruction set (RISC) principle. Currently, as another popular CPU architecture besides x86 and ARM, it is used in some edge devices. There is a small market.
Recently, Calista Redmond, CEO of RISC-V International, revealed at Embedded World that,There are already 10 billion RISC-V cores on the market.
Calista Redmond said that open standards are the key, “Linux is doing this for software, and we are doing this for hardware. We estimate that there are 10 billion RISC-V cores on the market.”
IT House learned that it took 17 years for the ARM architecture to reach this milestone in 2008, and RISC-V only about 12 years. Calista Redmond also wrote in the PPT,RISC-V CPU core count is expected to reach 80 billion by 2025.
On June 21, RISC-V International also announced the approval of the first four specifications and extensions for 2022 – RISC-V Efficient Trace (E-Trace), RISC-V Supervisor Binary Interface (SBI), RISC-V Unified Extensible Firmware Interface (UEFI) specification, and RISC-V Zmmul pure multiply extension.
Calista Redmond said: “RISC-V’s contribution and collaborative culture continue to yield impressive strategic results, and RISC-V members are leaders in the open computing era, proving that collaboration accelerates innovation through shared investment while increasing global opportunity.”
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