Micron 3D NAND Flash is entering new performance territory with 232 layers

From a technical point of view, Micron’s 232L-NAND is based on the same construction as the previous generation with a 176-layer design. It’s still a string-stacking design, with Micron relying on a pair of 116-layer decks in the form of “towers” versus 88 layers in the previous generation. 116-layer decks are notable in that Micron was the first to be able to produce a single deck with more than 100 layers, previously only available to Samsung but not yet available in volume.

Micron’s NAND decks continue to be built using the charge-trap CMOS under-array (CuA) architecture, where most of the NAND logic is placed under the NAND memory cells, giving an advantage in NAND density promises. According to the company, a density of 14.6 Gbit/mm² was achieved, which corresponds to a 43 percent higher density than 176L NAND and is between 35 and 100 percent higher than competing TLC products.

For SSDs: Micron 3D NAND flash launches into new performance territory with 232 layers (2)

Source: Micron

More storage space and performance

The improved density also allowed the manufacturer to produce its first 1TB TLC die, which allows Micron to now also produce 2TB chip packages by combining 16 of the 232L dies, benefitting larger SSD capacities but at smaller ones Sizes can be disadvantageous in terms of performance due to lower parallelism.

By increasing the number of planes in Micron’s NAND die from 4 to 6, the parallelism in each die has further improved. Quad-plane (four-plane) designs became common in the previous generation of NAND, and as NAND increases in density, so does the number of planes to allow transfer rates to keep up with the higher density.

Thanks to increased parallelism and improved internal transfer rates, Micron has been able to significantly increase its per-chip read and write speeds. According to the company, read speeds have improved by over 75 percent compared to the NAND generation 176L, while write speeds are said to have doubled. The chip housing has also been reduced by 28 percent, which is now 11.5 mm x 13.5 mm (~155 mm²) instead of 12 mm x 18 mm (216 mm²), which enables space savings or more components in the same space.

More energy efficiency and release

Micron has also implemented the new generation of ONFI (Standard Open NAND Flash Interface). The ONFI5.0, presented in 2021, increases the transfer rates between controller and NAND by 50 percent and brings them to 2,400 MT/s, matching current PCI-E 5.0 controllers. According to Micron, the NV-LPDDR4 signaling method introduced with ONFi 5.0 should also save more than 30 percent electricity per bit. The mass production of the new 3D NAND flash is said to have already started with delivery to the first customers and corresponding SSDs are already in the works.

Source: microns via Anandtech.com